The present invention relates to modeling the performance of an integrated circuit and, more particularly, to a system, a method and a computer program product for modeling the performance of an integrated circuit using a connectivity-based condensed resistance model for a conductive structure (e.g., a local interconnect, contact bar or other conductive structure) on a diffusion region of a semiconductor device in the integrated circuit.
Traditionally, the performance (i.e., behavioral characteristics, current-voltage (I-V) characteristics, etc.) of an integrated circuit is modeled by generating, from the design layout, full resistance models for all components of the integrated circuit including for all active devices, all passive devices and all interconnects within and between those active and passive devices. The component-level resistance models are used to generate component-level netlists and the component-level netlists are used to form a combined netlist for the integrated circuit itself. Simulations of the combined netlist are then performed over the full range of operating temperatures, over the full range of operating power supply voltages and, optionally, taking into consideration other factors that may impact performance (e.g., self-heating and stress). Additionally, repeated simulations may be required for model calibration and/or to accommodate design modifications or options. Based on the results of the simulations, a performance model for the integrated circuit is generated. Unfortunately, as the complexity of integrated circuits increases (i.e., as the number and complexity of active devices, passive devices and interconnects incorporated into integrated circuits increases), so does the amount of time and processing capability required to complete simulations and generate performance models. Therefore, there is a need for an improved and, particularly, faster method of accurately modeling the performance of an integrated circuit.